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rev: 2.05 6/2006 1/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8180dv18d-250/200/167/133/100 18mb burst of 4 sigmaquad sram 250 mhz?100 mhz 2.5 v v dd 1.8 v or 1.5 v i/o 165-bump bga commercial temp industrial temp features ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual doubledata rate interface ? byte write controls sampled at data-in time ? burst of 4 read and write ? 2.5 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq mode pin for programmable output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump, 13 mm x 15 mm, 1 mm bump pitch bga package ? pin-compatible with future 36mb, 72mb, and 144mb devices ? rohs-compliant 165-bump bga package available sigmaram ? family overview gs8180dv18 are built in compliance with the sigmaquad sram pinout standard for separate i/o synchronous srams. they are18,874,368-bit (18mb) sr ams. these are the first in a family of wide, very low voltage hstl i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. sigmaquad srams are offered in a number of configurations. some emulate and enhance other synchronous separate i/o srams. a higher performance sdr (single data rate) burst of 2 version is also offered. the logical differences between the protocols employed by these rams hinge mainly on various combinations of addr ess bursting, output data registering, and write cueing. along with the common i/o family of sigmarams, the sigmaquad family of srams allows a user to implement the interface protocol best suited to the task at hand. clocking and addr essing schemes a burst of 4 sigmaquad sram is a synchronous device. it employs two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. the device also allows the user to manipulate the output register clock inputs quasi independently with the c and c clock inputs. c and c are also independent single-ended clock inputs, not differential inputs. if the c clocks are tied high, the k clocks are routed internally to fire the output registers instead. because separate i/o burst of 4 rams always transfer data in four packets, a0 and a1 are intern ally set to 0 for the first read or write transfer, and automati cally incremented by 1 for the next transfers. because the lsbs are tied off internally, the address field of a burst of 4 ram is always two address pins less than the advertised index depth (e.g., the 1m x 18 has a 256k addressable index). parameter synopsis -250 -200 -167 -133 -100 tkhkh 4.0 ns 5.0 ns 6.0 ns 7.5 ns 10 ns tkhqv 2.1 ns 2.3 ns 2.5 ns 3.0 ns 3.0 ns n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
1m x 18 sigmaquad sram ?top view (package d) 1 2 3 4 5 6 7 8 9 10 11 a nc mcl/sa (144mb) nc/sa (36mb) w bw1 k nc r sa mcl/sa (72mb) nc b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h nc v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. expansion addresses: a3 for 36mb, a10 for 72mb, a2 for 144mb 2. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 3. mcl = must connect low 4. it is recommended that h1 be tied low for compatibility with future devices. gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 2/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
pin description table symbol description type comments sa synchronous address inputs input ? nc no connect ? ? r synchronous read input active low w synchronous write input active low bw0 ? bw1 synchronous byte writes input active low k input clock input active high k input clock input active low c output clock input active high c output clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? mcl must connect low ? ? d0?d17 synchronous data inputs input ? q0?q17 synchronous data outputs output ? v dd power supply supply 2.5 v nominal v ddq isolated output buffer supply supply 1.8 or 1.5 v nominal v ss power supply: ground supply ? gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 3/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: nc = not connected to die or any other pin background separate i/o srams, from a system architect ure point of view, are attractive in appli cations where alternating reads and writes are needed. therefore, the sigmaqua d sram interface and truth table are optimized fo r alternating reads and writes. separate i/o srams are unpopular in applicatio ns where multiple reads or multiple writes are n eeded because burst read or write transfers fr om separate i/o srams can cut the ram?s bandwidth in half. a sigmaquad sram can begin an alternating se quence of reads and writes with either a r ead or a write. in order for any separate i/o sram that shares a common address be tween its two ports to keep both ports running all the time, the ram must implement some sort of burst transfer pr otocol. the burst must be at l east long enough to co ver the time the oppo site port is receiving instructions on what to do next. the rate at which a ram can accept a new random addr ess is the most fund amental performance metric for the ram. each of the thr ee sigmaquad srams support si milar address rates because random address rate is determined by the internal performance of the ram and they are all based on the same internal circuits. di fferences between the truth tables of the different sigmaquad srams, or any other separate i/o srams, follow from differences in how the ram?s n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 4/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. interface is contrived to interact with the rest of the system. each mode of operation has its own advantages and disadvantages . the user should consider the nature of the work to be done by the ram to evaluate which version is best suited to the application a t hand. alternating read-write operations sigmaquad srams follow a few simple rules of operation. - read or write commands issued on one port are never allo w ed to interrupt an operation in progress on the other port. - read or write data transfers in progress may not be interrupted and re-started. - r and w high always deselects the ram. - all address, data, and control i nputs are sampled on clock edges. in order to enforce these rules, each ra m combines present state in formation with command inputs. see the truth table for details. burst of 4 sigmaquad sram ddr read the status of the address input, w , and r pins are sampled at each rising edge of k. w and r high causes chip disable. a low on the read enable-bar pin, r , begins a read cycle. r is always ignored if the previous co mmand loaded was a r ead command. the four resulting data output transfers begin after the next rising e dge of the k clock. data is clocked out by the next rising e dge of the c, the rising edge of c after that, the next rising edge of c, and finally by the next rising edge of c . burst of 4 double data rate sigmaquad sram read first read a nop read b write c read d write e nop a b c d e c c+1 c+2 c+3 e e+1 c c+1 c+2 c+3 e e+1 a a+1 a+2 a+3 b b+1 b+2 b+3 d d+1 d+2 k k address r w bwx d c c q n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 5/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. burst of 4 sigmaquad sram ddr write the status of the address input, w , and r pins are sampled at each rising edge of k. w and r high causes chip disable. a low on the write enable-bar pin, w , and a high on the read enable-bar pin, r , begins a write cycle. w is always ignored if the previous command was a write command. data is clocked in by the next rising edge of k, the rising edge of k after that, the next rising edge of k, and finally by the next rising edge of k . burst of 4 double data rate sigmaquad sram write first write a nop write b read c nop read d nop a b c d a a+1 a+2 a+3 b b+1 b+2 b+3 a a+1 a+2 a+3 b b+1 b+2 b+3 c c+1 c+2 c+3 d k k address r w bwx d c c q special functions byte write control byte write enable pins are sampled at the same time that data in is sampled. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of th at particular byte, leaving whatever data may be stored at the cu rrent address at that byte location undisturbed. any or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and wr ite address loaded into the ram provides the base address for a 4 beat data transfer. the x18 version of the ram, for example, may write 72 bits in association with each address loaded. any 9-bit byte may be masked in any write sequence. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
example x18 ram write sequen ce using byte write enables data in sample ti me bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in beat 3 0 0 data in data in beat 4 1 0 don?t care data in resulting write operation beat 1 d0?d8 beat 1 d9?d17 beat 2 d0?d8 beat 2 d9?d17 beat 3 d0?d8 beat 3 d9?d17 beat 4 d0?d8 beat 4 d9?d17 written unchanged unchanged written written written unchanged written gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 6/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. output register control sigmaquad srams offer two mechanisms for controlling the output data registers. typically, control is handled by the output r egister clock inputs, c and c . the output register clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds be yond the next rising edges of th e k and k clocks. if the c and c clock inputs are tied high, the ram reverts to k and k control of the outputs, allowing the ram to function as a conventional pipelined read sram. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
a k r w a 0 ?a n k w 0 d 1 ?d n bank 0 bank 1 bank 2 bank 3 r 0 d a k w d a k w d a k w d r r r qqq q cc cc q 1 ?q n c w 1 r 1 w 2 r 2 w 3 r 3 note: for simplicity bwn , k , and c are not shown. gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 7/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. example four bank dept h expansion schematic n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
burst of 4 sigmaquad sram depth expansion read a write b read c write d read e write f nop a b c d e f d d+1 d+2 d+3 d d+1 d+2 d+3 b b+1 b+2 b+3 f f+1 f+2 b b+1 b+2 b+3 f f+1 f+2 a a+1 a+2 a+3 e e+1 e+2 c c+1 c+2 c+3 k k address r1 r2 w1 w2 bwx bank1 d bank1 bwx bank2 d bank2 c bank1 c bank1 q bank1 c bank2 c bank2 q bank2 gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 8/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 9/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. flxdrive-ii output driver impedance control hstl i/o sigmaquad srams are supplied with programmable impeda nce output drivers. the zq pi n must be connected to v ss via an external resistor, rq, to allow the sram to monitor and adjust its output driver impedance. the value of rq must be 5x t he value of the intended line impedance driven by the sram. the allowable range of rq to guaran tee impedance matching with a vendor-specified tolera nce is between 150 ? and 300 ? . periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. a clock cycle c ounter periodically triggers an impedance evaluation, resets and counts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps. the sram requires 32k start-up cycles, selected or deselected, after v dd reaches its operating range to reac h its programmed output driver impedance. separate i/o burst of 4 si gmaquad sram truth table a r w previous operation current operation d d d d q q q q k (t n ) k (t n ) k (t n ) k (t n-1 ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) x 1 1 deselect deselect x x ? ? hi-z hi-z ? ? x 1 x write deselect d2 d3 ? ? hi-z hi-z ? ? x x 1 read deselect x x ? ? q2 q3 ? ? v 1 0 deselect write d0 d1 d2 d3 hi-z hi-z ? ? v 0 x deselect read x x ? ? q0 q1 q2 q3 v x 0 read write d0 d1 d2 d3 q2 q3 ? ? v 0 x write read d2 d3 ? ? q0 q1 q2 q3 notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v ? = input ?valid?; ?x? = input ?don?t care? 2. ??? indicates that the input requirement or output state is determined by the next operation. 3. q0, q1, q2, and q3 indicate the first, second, third, and f ourth pieces of output da ta transferred during read operations. 4. d0, d1, d2, and d3 indicate the first, second, third, and fourt h pieces of input data transferred during write operations. 5. qs are tristated for one cycle in response to deselect and write commands, one cycle after the command is sampled, except whe n pre- ceded by a read command. 6. users should not clock in metastable addresses. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
byte write clock truth table bw bw bw bw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) t t t t write dx stored if bwn = 0 in all four data transfers d0 d2 d3 d4 t f f f write dx stored if bwn = 0 in 1st data transfer only d0 x x x f t f f write dx stored if bwn = 0 in 2nd data transfer only x d1 x x f f t f write dx stored if bwn = 0 in 3rd data transfer only x x d2 x f f f t write dx stored if bwn = 0 in 4th data transfer only x x x d3 f f f f write abort no dx stored in any of the four data transfers x x x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?d on?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 10/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 11/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. state diagram power- read nop load new read address r count = 0 ddr read r count = r count + 1 write nop load new write address w count = 0 ddr write w count = w count + 1 write read read r count = 2 write w count = 2 read write always always read r count = 2 notes: 1. internal burst counter is fixed as 2- bit linear (i.e., when first address is a0), next internal burst address is a0+1. 2. ?read? refers to read active status with r = low, ?read ? refers to read inactive status with r = high. the same is true for ?write? and ?write ?. 3. read and write state machine can be active simultaneously. 4. state machine control timi ng sequence is controlled by k. 5. r count is the read counter; burst of 4 must complete 2 ddr reads. 6. w count is the write counter; burst of 4 must complete 2 ddr writes. read r count = 1 always increment read address write w count = 2 increment write address write w count = 1 always n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 3.6 v v ddq voltage in v ddq pins ?0.5 to 3.6 v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 12/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. recommended oper ating conditions power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 2.4 2.5 2.6 v 1.8 v i/o supply voltage v ddq 1.7 1.8 1.95 v 1 1.5 v i/o supply voltage v ddq 1.4 1.5 1.6 v 1 ambient temperature (commercial range versions) t a 0 25 70 notes: 1. unless otherwise noted, all perfo rmance sp ecifications quoted are evaluated for worst case at both 1.4 v , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . 3. most speed grades and configurations of this device are of fered in both commercial and indus trial t emperature ranges. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all per formance specifications quoted a re evaluated for worst case in the temperature range marked on the device. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 13/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. hstl i/o dc input characteristics parameter symbol min max units notes dc input logic high v ih (dc) v ref + 200 mv 1 dc input logic low v il (dc) v ref ? 200 mv 1 v ref dc voltage v ref (dc) v ddq (min)/2 v ddq (max)/2 v 1 note: compatible with both 1.8 v and 1.5 v i/o drivers hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 400 mv 3,4 ac input logic low v il (ac) v ref ? 400 mv 3,4 v ref peak to peak ac voltage v ref (ac) 5% v ref (dc) mv 1 notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. to guarantee ac characteristics, v ih ,v il , trise, and tfall of inputs and clocks must be within 10% of each other. 3. for devices supplied with hstl i/o input buffers. compatible with both 1.8 v and 1.5 v i/o drivers. 4. see ac input definition drawing below. v ih (ac) v ref v il (ac) hstl i/o ac i nput definitions n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 14/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 20% tkhkh v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkhkh v dd + 1.0 v 50% v dd v il capacitance o c, f = 1 mh z , v dd parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf note: this parameter is sample tested. ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 notes: test conditions as specified with outpu t loading as shown unless othe rwise noted. dq vt = v ddq /2 50? rq = 250 ? (hstl i/o) v ref = 0.75 v ac test load diagram (t a = 25 = 3.3 v) n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 15/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 v ddq v 1, 3 output low voltage v ol1 vss v ddq /2 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175 ? rq 350 ?). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? rq 350 ?) . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v or 1.8 v 4. minimum impedance mode, zq = v ss 5. i oh = ?1.0 ma 6. i ol = 1.0 ma n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
operating currents parameter org symbol -250 -200 -167 -133 -100 test conditions 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current x18 idd 430 ma 440 ma 365 ma 375 ma 320 ma 330 ma 275 ma 285 ma 255 ma 265 ma r and w v il max. tkhkh tkhkh min. all other inputs v in v il max. or v in v ih min. iddq 215 ma 225 ma 210 ma 220 ma 190 ma 200 ma 170 ma 180 ma 150 ma 160 ma chip dis able current x18 isb1 150 ma 160 ma 135 ma 145 ma 130 ma 140 ma 120 ma 130 ma 110 ma 120 ma r and w v ih min. tkhkh tkhkh min. all other inputs v in v il max. or v in v ih min. isbq1 40 ma 45 ma 40 ma 45 ma 35 ma 40 ma 35 ma 40 ma 25 ma 35 ma note: power measured with output pins floating. gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 16/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
ac electrical characteristics parameter symbol -250 -200 -167 -133 -100 units notes min max min max min max min max min max k, k clock cycle time c, c clock cycle time t khkh t chch 4.0 ? 5.0 ? 6.0 ? 7.5 ? 10 ? ns k, k clock high pulse width c, c clock high pulse width t khkl t chcl 1.5 ? 1.9 ? 2.4 ? 3.0 ? 3.0 ? ns k, k clock low pulse width c, c clock low pulse width t klkh t clch 1.5 ? 1.9 ? 2.4 ? 3.0 ? 3.0 ? ns k clock high to k clock high c clock high to c clock high t kh k h t ch c h 1.8 2.2 2.7 ? 3.4 ? 4.6 ns 4 k clock high to k clock high c clock high to c clock high t k hkh t c hch 1.8 2.2 2.7 ? 3.4 ? 4.6 ns k, k clock high to c, c clock high t khch 0 1.4 0 1.7 0 2.0 0 2.5 0 3.0 ns address input setup time t avkh 0.5 ? 0.6 ? 0.7 ? 0.8 ? 1.0 ? ns address input hold time t khax 0.5 ? 0.6 ? 0.7 ? 0.8 ? 1.0 ? ns control input setup time t bvkh 0.5 ? 0.6 ? 0.7 ? 0.8 ? 1.0 ? ns 1 control input hold time t khbx 0.5 ? 0.6 ? 0.7 ? 0.8 ? 1.0 ? ns 1 data and byte write input setup ti me t dvkh 0.5 ? 0.6 ? 0.7 ? 0.8 ? 1.0 ? ns data and byte write input hold time t khdx 0.5 ? 0.6 ? 0.7 ? 0.8 ? 1.0 ? ns k, k clock high to data output valid c, c clock high to data output valid t khqv t chqv ? 2.1 ? 2.3 ? 2.5 ? 3.0 ? 3.0 ns k, k clock high to data output hold c, c clock high to data output hold t khqx t chqx 0.5 ? 1.0 ? 1.2 ? 1.2 ? 1.2 ? ns 2 k clock high to data output low-z c clock high to data output low-z t khqx1 t chqx1 0.5 ? 1.0 ? 1.2 ? 1.2 ? 1.2 ? ns 2,3 k clock high to data output high-z c clock high to data output high-z t khqz t chqz 0.5 2.1 ? 2.3 ? 2.5 ? 3.0 ? 3.0 ns 2,3 notes: 1. these parameters apply to control inputs r and w . 2. these parameters are guaranteed by design and characterization. not 100% tested. 3. these parameters are measured at 50mv from stea dy state voltage. 4. t kh k h max is specified by t k hkh min. t ch c h max is specified by t c hch min. gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 17/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 18/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. k and k controlled read-wri te-read timing diagram read a write b nop write c read d write e nop a b c d e b b+1 b+2 b+3 c c+1 c+2 c+3 e e+1 b b+1 b+2 b+3 c c+1 c+2 c+3 e e+1 a a+1 a+2 a+3 d d+1 d+2 d+3 khqz khqx khqv khqx1 khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khkh klkhklkh khklkhkl khkhkhkh k k address r w bwx d q n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 19/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. c and c controlled read-wri te-read timing diagram read a nop read b write c nop write d nop a b c d c c+1 c+2 c+3 d d+1 c c+1 c+2 c+3 d d+1 a a+1 a+2 a+3 b b+1 b+2 b+3 chqz chqx chqv chqx1 khkh khkl klkh khkl klkh khkhkhkh khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khkh klkhklkh khklkhkl khkhkhkh k k address r w bwx d c c q n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 20/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. jtag port operation overview the jtag port on this ram operates in a manner that is co mpliant with i eee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input interface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captur ed on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck . this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the ri sing edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register plac ed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in res ponse to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap c ontroller is also reset automaticly at power-up. jtag port registers overview the various jtag registers, refered to as te st access port ortap registers, are selected (one at a time) vi a the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck an d pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. the instruction regist er can be loaded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in th e scan chain with as li ttle delay as possible. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 21/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then da isy chained together so the levels found can be shif ted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder fl ip flops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is desc ribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the co ntents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be used to activate the b oundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specifi c 32-bit code when the controller is put in capture-dr state with th e idcode command loaded in the inst ruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
id register contents not used gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1 gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 22/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. tap controller instruction set overview there are two classes of instructions defi ned in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instru ctions are mandatory for 1149 .1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift- ir state the instruction regi ster is placed between tdi an d tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instru ction set for this device is listed in the following table. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 1 1 1 gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 23/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regist er is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the boa rd level scan path to be shortened to facili - tate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public in structi on. when the sample / preload instruction is loaded in the instruction regist er, moving the tap controller into the capture- dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state identified in the boundary scan chain table at the end of this section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/ o ring contents into th e boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override the ram?s input pins; therefore, the ram?s internal state is n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 24/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. still determined by its input pins. typically, the boundary scan register is load ed with the desired pattern of data with the sample/preload command. then the extest command is used to output the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when th e controller is in the update-ir state. alternately, the boundary scan regist er may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram? s inp ut and i/o pins, as well as the default values at scan regi ster locations not as so - ciated with a pin, are transferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundary scan register location with which each output pin is associ - ated. idcode the idcode instructi on caus es the id rom to be loaded into the id regist er when the controller is in capture-dr mode and places the id register between the tdi an d tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction regist er , all ram outputs are forced to an inactive drive state (high- z) and the boundary scan register is connected between tdi and td o when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan regi ster between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypas s register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypas s register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up a nd in test-logic-reset state. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 25/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. jtag port recommended operating co nditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj ? 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.6 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj 1.7 ? v 5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v 5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 1 v < v i < v ddn +1 v not to exceed 3.6 maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj ddn 3. 0 v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50? 30pf * jtag port ac test load * distributed test jig capacitance n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 26/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 27/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. package dimensions?165- bump fpbga (package d) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 130.05 150.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.20 c 0.36~0.46 1.40 max. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t
ordering informati on?gsi sigmaquad sram org part number 1 type package speed (mhz) t a 2 status 3 1m x 18 gs8180dv18d-250 sigmaquad sram 165-pin bga 250 c mp 1m x 18 gs8180dv18d-200 sigmaquad sram 165-pin bga 200 c mp 1m x 18 gs8180dv18d-167 sigmaquad sram 165-pin bga 167 c mp 1m x 18 gs8180dv18d-133 sigmaquad sram 165-pin bga 133 c mp 1m x 18 gs8180dv18d-100 sigmaquad sram 165-pin bga 100 c mp 1m x 18 gs8180dv18d-250i sigmaquad sram 165-pin bga 250 i mp 1m x 18 gs8180dv18d-200i sigmaquad sram 165-pin bga 200 i mp 1m x 18 gs8180dv18d-167i sigmaquad sram 165-pin bga 167 i mp 1m x 18 GS8180DV18D-133I sigmaquad sram 165-pin bga 133 i mp 1m x 18 gs8180dv18d-100i sigmaquad sram 165-pin bga 100 i mp 1m x 18 gs8180dv18gd-200 sigmaquad sram rohs-compliant 165-pin bga 200 c mp 1m x 18 gs8180dv18gd-167 sigmaquad sram rohs-compliant 165-pin bga 167 c mp 1m x 18 gs8180dv18gd-133 sigmaquad sram rohs-compliant 165-pin bga 133 c mp 1m x 18 gs8180dv18gd-100 sigmaquad sram rohs-compliant 165-pin bga 100 c mp 1m x 18 gs8180dv18gd-250i sigmaquad sram rohs-compliant 165-pin bga 250 i mp 1m x 18 gs8180dv18gd-200i sigmaquad sram rohs-compliant 165-pin bga 200 i mp 1m x 18 gs8180dv18gd-167i sigmaquad sram rohs-compliant 165-pin bga 167 i mp 1m x 18 gs8180dv18gd-133i sigmaquad sram rohs-compliant 165-pin bga 133 i mp 1m x 18 gs8180dv18gd-100i sigmaquad sram rohs-compliant 165-pin bga 100 i mp notes: 1. customers requiring delivery in tape and reel should add the c haracter ?t? to the end of the part number . example: gs818x18d- 200t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range. 3. mp = mass production. gs8180dv18d-250/200/167/133/100 rev: 2.05 6/2006 28/28 ? 2002, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. n o t r e c o m m e n d e d f o r n e w d e s i g n ?d i s c o n t i n u e d p r o d u c t

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